Verilog Source Code Formatter
The VerilogFormatter tool reorganizes Verilog source text files to neatly indent code blocks according to their nesting level. It is a member of SD's family of Source Code Formatters. An example of the Verilog Formatter's results can be seen here.
Verilog Formatter Features
- Formatted code compiles and synthesizes exactly like unformatted code
- Handles full Verilog 2001
- Specification of indentation step distance
- Specification of arbitrary input tab column positions
- A version with obfuscation capability can make it difficult to understand by renaming variables and removing all formatting.
